Metal oxide semiconductor field effect transistor (MOSFET) devices fabricated on SOI (silicon on insulator) substrates offer advantages of low-voltage and high speed operation. SOI-MOSFETs have a comparatively simple construction and a smaller layout as compared with bulk silicon transistor devices. SOI transistors have therefore become increasingly popular in today's semiconductor manufacturing industry where there is a constant push to reduce the layout size of devices and increase device speed and performance.
SOI-MOSFET and other SOI transistor devices are formed on substructures that include an upper silicon layer formed over an oxide layer formed over a bulk substrate. To achieve better short channel effects, the silicon layer atop the oxide layer is formed to be very thin.
SOI-MOSFET devices, other MOSFET devices and other semiconductor device transistors benefit from strain enhancement in the source/drain regions. This is true for PMOS and NMOS technologies. The increased strain is known to improve device performance and device speed. Source/drain regions of transistors are generally formed in the substrate over which the transistor gate is formed and for SOI-MOSFET devices, the source/drain regions are formed in the upper silicon layer.
With the source/drain regions formed in the necessarily thin upper silicon layer, one shortcoming of SOI transistor devices is the inability to improve device performance by introducing strain materials in the source/drain regions.